Marine Laboratory

Intelligent Design and Application Laboratory
(IDA Lab)

Multi-domain Innovation with AI at the Core:
Intelligent Solutions for VLSI Design, Hardware Security, and Healthcare

Laboratory Overview

The Intelligent Design and Application Laboratory (IDA Lab) at National Taiwan Ocean University is dedicated to advancing research in the intersection of artificial intelligence and various application domains including VLSI design, hardware security, and healthcare.

Our mission is to develop innovative solutions through the application of cutting-edge AI technologies to solve complex problems across multiple domains. We focus on translating theoretical advancements into practical applications with real-world impact.

Led by Dr. Chia-Heng Yen, our team consists of talented researchers and students from diverse backgrounds, working collaboratively on interdisciplinary projects that bridge the gap between technology and application domains.

Research Highlights

AI Icon

AI-driven VLSI Design

Optimizing integrated circuit testing and design processes through advanced machine learning techniques.

Security Icon

Hardware Security

Enhancing chip security through innovative detection and protection mechanisms for hardware trojans.

Medical Icon

Medical Imaging

Developing advanced algorithms for cancer prediction and diagnosis using medical image analysis.

Circuit Icon

Digital Circuit Design

Creating optimized circuit designs with innovative architectures for better performance and power efficiency.

Latest Announcements

Graduate Student Recruitment

We are currently recruiting Master's students. If you are interested in Electronic Design Automation, Digital Design, Intelligent Application, and Intelligent Healthcare, please feel free to contact me.

2025/02/27

Principal Investigator

Professor Photo

Dr. Chia-Heng Yen

Assistant Professor at Department of Computer Science and Engineering

National Taiwan Ocean University

Email Icon Email: chyen[at]mail.ntou.edu.tw
Phone Icon Tel: +886-2-2462-2192 #6679
Office Icon Office: ECG 703
Lab Icon IDA Lab: ECG 810

Education

Doctor of Philosophy (Ph.D.) in Computer Science and Engineering

National Yang Ming Chiao Tung University (NYCU)

Laboratory: Computer-Aided Design for G(reen)-RE(liable)-A(nd)-T(rustworthy) (GREAT) Systems Lab.

Advisor: Prof. Kai-Chiang Wu

Doctoral Dissertation: Machine Learning-Based IC Testing – Reliability and Security Perspectives

Master of Science (M.S.) in Bioinformatics and Systems Biology

National Chiao Tung University (NCTU) (currently National Yang Ming Chiao Tung University)

Laboratory: Intelligent Computing Lab.

Advisor: Distinguished Prof. Shinn-Ying Ho

Master's Thesis: Prediction of Recurrence Time after Therapeutic Surgery Using CT Images on Liver Tumor

Bachelor of Science (B.S.) in Computer Science and Engineering

National Taiwan Ocean University (NTOU)

Research Topics

IC Testing and Yield Enhancement

Our research in IC testing addresses two key challenges through AI techniques. First, we develop CNN-based stochastic regression methods for IDDQ outlier identification, effectively distinguishing leakage current variations from actual defects in IC testing. Second, we address the neighborhood effect problem in wafer testing through innovative methods to identify Good-Dice-in-Bad-Neighborhoods (GDBN), integrating wafer-level defect pattern information with advanced machine learning models ranging from CNNs to Transformer architectures. Both approaches significantly improve testing accuracy, yield rates, and cost efficiency.

Related Publications

2024 Chia-Heng Yen, Ting-Rui Wang, Ching-Min Liu, Cheng-Hao Yang, Chun-Teng Chen, et al., "Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks," IEEE Transactions on Semiconductor Manufacturing (TSM), vol. 37, no. 3, pp. 280—292
2023 Chia-Heng Yen, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, et al., "CNN-based Stochastic Regression for IDDQ Outlier Identification," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 42, no. 11, pp. 4282—4295
2024 Cheng-Che Lu, Chi-Chih Chang, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, et al., "Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods," IEEE VLSI Test Symposium (VTS), pp. 1—7
2023 Ching-Min Liu, Chia-Heng Yen, Shu-Wen Lee, Kai-Chiang Wu and Mango Chia-Tso Chao, "Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information," IEEE International Test Conference (ITC), pp. 357—366
2021 Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, et al., "Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks," IEEE VLSI Test Symposium (VTS), pp. 1—6
2020 Chun-Teng Chen, Chia-Heng Yen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, et al., "CNN-Based Stochastic Regression for IDDQ Outlier Identification," IEEE VLSI Test Symposium (VTS), pp. 1—6

Medical Image Analysis and Cancer Prediction

Application of machine learning and deep learning techniques to medical image analysis, with particular focus on cancer prediction. This research demonstrates the perfect integration of technology and clinical applications, bridging the gap between advanced AI technologies and real-world medical challenges in cancer diagnosis and prognosis.

Related Publications

2024 I-Cheng Lee, Yung-Ping Tsai, Yen-Cheng Lin, Ting-Chun Chen, Chia-Heng Yen, et al., "A Hierarchical Fusion Strategy of Deep Learning Networks for Detection and Segmentation of Hepatocellular Carcinoma from Computed Tomography Images," Cancer Imaging, vol. 24, no. 1, Art. no. 43
2023 Tzu-Ting Huang, Yi-Chen Lin, Chia-Heng Yen, Jui Lan, Chiun-Chieh Yu, et al., "Prediction of Extranodal Extension in Head and Neck Squamous Cell Carcinoma by CT Images Using an Evolutionary Learning Model," Cancer Imaging, vol. 23, no. 1, Art. no. 84
2021 I-Cheng Lee, Jo-Yu Huang, Ting-Chun Chen, Chia-Heng Yen, Nai-Chi Chiu, et al., "Evolutionary Learning Derived Clinical-Radiomic Models for Predicting Early Recurrence of Hepatocellular Carcinoma After Resection," Liver Cancer, vol. 10, no. 6, pp. 572—582
2018 Tzu-Yun Lo, Pei-Yin Wei, Chia-Heng Yen, Jiing-Feng Lirng, Muh-Hwa Yang and Pen-Yuan Chu, "Prediction of Metastasis in Head and Neck Cancer from Computed Tomography Images," International Conference on Robotics and Artificial Intelligence (ICRAI), pp. 18—23

Hardware Security and Trojan Detection

An emerging research direction focusing on using machine learning techniques to enhance chip security. We apply cutting-edge graph neural network technologies (GCN and GAT) to address critical security problems of hardware trojan detection and localization, providing comprehensive protection mechanisms for hardware security.

Related Publications

2024 Yu-Chen Hsiao, Chia-Heng Yen, Bo-Yang Ke and Kai-Chiang Wu, "Synergizing GCN and GAT for Hardware Trojan Detection and Localization," IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S), pp. 161—162
2023 Chia-Heng Yen, Jung-Che Tsai and Kai-Chiang Wu, "Using Path Features for Hardware Trojan Detection Based on Machine Learning Techniques," International Symposium on Quality Electronic Design (ISQED), pp. 1—8

Arithmetic Design and Digital Circuits

Focused on high-performance digital circuit design, particularly innovation and optimization of adder architectures. Our sum-prediction adder research targets the most commonly used basic computational units in modern processors, achieving a balance between speed, power consumption, and area through clever architectural optimization. This research not only focuses on theoretical performance improvements but also considers engineering constraints in practical application environments.

Related Publications

2024 Chia-Heng Yen and Jin-Tai Yan, "Design and Analysis of Sum-Prediction Adder," Integration - the VLSI Journal, vol. 96, Art. no. 102139

Electronic Design Automation (EDA) and Circuit Optimization

This research direction encompasses both routing techniques and power optimization for integrated circuits. For routing, we address challenges in emerging materials such as graphene nanoribbons (GNR) and complex 3D integrated circuits. Our power optimization work focuses on multi-bit flip-flop (MBFF) utilization strategies to reduce clock power consumption, an increasingly critical concern in modern low-power designs.

Related Publications

2023 Chia-Heng Yen and Jin-Tai Yan, "Layer-Minimization-Oriented GNR Area Routing," IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1—4
2016 Jin-Tai Yan, Meng-Tian Chen and Chia-Heng Yen, "Cell-Aware MBFF Utilization for Clock Power Reduction," IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 648—651
2019 Jin-Tai Yan and Chia-Heng Yen, "Construction of Delay-Driven GNR Routing Tree," IEEE International New Circuits and Systems Conference (NEWCAS), pp. 1—4
2018 Jin-Tai Yan and Chia-Heng Yen, "Feasible Assignment of Micro-Bumps in 3D ICs," IEEE International New Circuits and Systems Conference (NEWCAS), pp. 296—299
2014 Jin-Tai Yan, Yu-Jen Tseng and Chia-Heng Yen, "Feasible Region Assignment of Routing Nets in Single-Layer Routing," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 393—396
2014 Jin-Tai Yan, Yu-Jen Tseng and Chia-Heng Yen, "Efficient Micro-Bump Assignment for RDL Routing in 3DICs," IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 195—198

Publications

2024

A Hierarchical Fusion Strategy of Deep Learning Networks for Detection and Segmentation of Hepatocellular Carcinoma from Computed Tomography Images
I-Cheng Lee, Yung-Ping Tsai, Yen-Cheng Lin, Ting-Chun Chen, Chia-Heng Yen, Nai-Chi Chiu, Hsuen-En Hwang, Chien-An Liu, Jia-Guan Huang, Rheun-Chuan Lee, Yee Chao, Shinn-Ying Ho and Yi-Hsiang Huang
Cancer Imaging, vol. 24, no. 1, Art. no. 43, Mar. 2024
SCI Deep Learning Medical Imaging
https://doi.org/10.1186/s40644-024-00686-8
Design and Analysis of Sum-Prediction Adder
Chia-Heng Yen and Jin-Tai Yan
Integration - the VLSI Journal, vol. 96, Art. no. 102139, May 2024
SCI VLSI Adder Design
https://doi.org/10.1016/j.vlsi.2024.102139
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks
Chia-Heng Yen, Ting-Rui Wang, Ching-Min Liu, Cheng-Hao Yang, Chun-Teng Chen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu and Mango Chia-Tso Chao
IEEE Transactions on Semiconductor Manufacturing (TSM), vol. 37, no. 3, pp. 280—292, Aug. 2024
SCI Neural Networks Semiconductor
https://doi.org/10.1109/TSM.2024.3406395
Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods
Cheng-Che Lu, Chi-Chih Chang, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu and Mango Chia-Tso Chao
In Proc. of IEEE VLSI Test Symposium (VTS), pp. 1—7, Apr. 2024
VLSI Transformer Testing
https://doi.org/10.1109/VTS60656.2024.10538654
Synergizing GCN and GAT for Hardware Trojan Detection and Localization
Yu-Chen Hsiao, Chia-Heng Yen, Bo-Yang Ke and Kai-Chiang Wu
In Proc. of IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S), pp. 161—162, Jun. 2024
Hardware Security Graph Neural Networks
https://doi.org/10.1109/DSN-S60304.2024.00047
Wafer-View Defect-Pattern-Prominent GDBN Method Using MetaFormer Variant
Shu-Wen Li, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu and Mango Chia-Tso Chao
In Proc. of IEEE International Test Conference (ITC), pp. 76—80, Oct. 2024
MetaFormer Defect Pattern Testing
https://doi.org/10.1109/ITC51657.2024.00023

2023

Prediction of Extranodal Extension in Head and Neck Squamous Cell Carcinoma by CT Images Using an Evolutionary Learning Model
Tzu-Ting Huang, Yi-Chen Lin, Chia-Heng Yen, Jui Lan, Chiun-Chieh Yu, Wei-Che Lin, Yueh-Shng Chen, Cheng-Kang Wang, Eng-Yen Huang and Shinn-Ying Ho
Cancer Imaging, vol. 23, no. 1, Art. no. 84, Sep. 2023
SCI Medical Imaging Evolutionary Learning
https://doi.org/10.1186/s40644-023-00601-7
CNN-based Stochastic Regression for IDDQ Outlier Identification
Chia-Heng Yen, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu and Mango Chia-Tso Chao
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 42, no. 11, pp. 4282—4295, Nov. 2023
SCI CNN Integrated Circuits
https://doi.org/10.1109/TCAD.2023.3253043
Using Path Features for Hardware Trojan Detection Based on Machine Learning Techniques
Chia-Heng Yen, Jung-Che Tsai and Kai-Chiang Wu
In Proc. of International Symposium on Quality Electronic Design (ISQED), pp. 1—8, Apr. 2023
Hardware Security Machine Learning
https://doi.org/10.1109/ISQED57927.2023.10129300
Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information
Ching-Min Liu, Chia-Heng Yen, Shu-Wen Lee, Kai-Chiang Wu and Mango Chia-Tso Chao
In Proc. of IEEE International Test Conference (ITC), pp. 357—366, Oct. 2023
Defect Pattern Testing
https://doi.org/10.1109/ITC51656.2023.00053
Layer-Minimization-Oriented GNR Area Routing
Chia-Heng Yen and Jin-Tai Yan
In Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1—4, Dec. 2023
Routing GNR
https://doi.org/10.1109/ICECS58634.2023.10382834

2021

Evolutionary Learning Derived Clinical-Radiomic Models for Predicting Early Recurrence of Hepatocellular Carcinoma After Resection
I-Cheng Lee, Jo-Yu Huang, Ting-Chun Chen, Chia-Heng Yen, Nai-Chi Chiu, Hsuen-En Hwang, Jia-Guan Huang, Chien-An Liu, Gar-Yang Chau, Rheun-Chuan Lee, Yi-Ping Hung, Yee Chao, Shinn-Ying Ho and Yi-Hsiang Huang
Liver Cancer, vol. 10, no. 6, pp. 572—582, Sep. 2021
SCI Evolutionary Learning Medical Imaging
https://doi.org/10.1159/000518728
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks
Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu and Mango Chia-Tso Chao
In Proc. of IEEE VLSI Test Symposium (VTS), pp. 1—6, Apr. 2021
Neural Networks VLSI Testing
https://doi.org/10.1109/VTS50974.2021.9441055

2020

CNN-Based Stochastic Regression for IDDQ Outlier Identification
Chun-Teng Chen, Chia-Heng Yen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao and Mango Chia-Tso Chao
In Proc. of IEEE VLSI Test Symposium (VTS), pp. 1—6, Apr. 2020
CNN VLSI Testing
https://doi.org/10.1109/VTS48691.2020.9107570

2019

Construction of Delay-Driven GNR Routing Tree
Jin-Tai Yan and Chia-Heng Yen
In Proc. of IEEE International New Circuits and Systems Conference (NEWCAS), pp. 1—4, Jun. 2019
Routing GNR
https://doi.org/10.1109/NEWCAS44328.2019.8961288

2018

Feasible Assignment of Micro-Bumps in 3D ICs
Jin-Tai Yan and Chia-Heng Yen
In Proc. of IEEE International New Circuits and Systems Conference (NEWCAS), pp. 296—299, Jun. 2018
3D IC Micro-Bump
https://doi.org/10.1109/NEWCAS.2018.8585566
Prediction of Metastasis in Head and Neck Cancer from Computed Tomography Images
Tzu-Yun Lo, Pei-Yin Wei, Chia-Heng Yen, Jiing-Feng Lirng, Muh-Hwa Yang, Pen-Yuan Chu and Shinn-Ying Ho
In Proc. of International Conference on Robotics and Artificial Intelligence (ICRAI), pp. 18—23, Nov. 2018
Medical Imaging Machine Learning
https://doi.org/10.1145/3297097.3297108

2016

Cell-Aware MBFF Utilization for Clock Power Reduction
Jin-Tai Yan, Meng-Tian Chen and Chia-Heng Yen
In Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 648—651, Dec. 2016
Clock Power MBFF
https://doi.org/10.1109/ICECS.2016.7841285

2014

Feasible Region Assignment of Routing Nets in Single-Layer Routing
Jin-Tai Yan, Yu-Jen Tseng and Chia-Heng Yen
In Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 393—396, Jun. 2014
Routing Single-Layer
https://doi.org/10.1109/ISCAS.2014.6865148
Efficient Micro-Bump Assignment for RDL Routing in 3DICs
Jin-Tai Yan, Yu-Jen Tseng and Chia-Heng Yen
In Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 195—198, Dec. 2014
3D IC RDL Routing
https://doi.org/10.1109/ICECS.2014.7049955

Teaching Courses

B5701R9E
Digital Logic
Semester: Spring 2025 Time: Tuesday 13:10-16:00 Location: ECG B107

This course covers the fundamental concepts of digital logic design, including Boolean algebra, logic gates, combinational and sequential circuits, optimization techniques, and introduction to digital systems.

B5701R9F
Laboratory of Digital Design
Semester: Spring 2025 Time: Wednesday 13:10-16:00 Location: ECG 610

A hands-on laboratory course focuses on digital logic design using breadboards and Computer-Aided Design (CAD) tools. The course emphasizes practical skills in digital logic design, including circuit construction and debugging, and design verification.

Lab Members

Ph.D. Students

Master Students

Undergraduate Students

Alumni